As semiconductor devices continue to advance and become more highly integrated and as the device features become increasingly miniaturized, the alignment between one device level and another device level increases in criticality. The patterns that combine to form integrated circuit or other semiconductor devices must be accurately and precisely aligned to one another, i.e. each pattern must be properly overlaid with respect to existing patterns. Embedded flash products represent one particular example of a product that requires stringent overlay control at various levels such as the floating gate level, in order to minimize program state leakage. While such embedded flash products may be particularly sensitive to overlay accuracy, it is important to accurately align every device level of every semiconductor device with each of the previously formed device levels, so that each device level functions as intended, in conjunction with each subjacent layer.
In conventional processing, overlay accuracy is typically measured using optical metrology tools. Such optical measurements are time consuming and subject to inaccuracies due to optical metrology limitations. Since the time-consuming optical measurements are typically required to be fed back to the exposure tool, only a limited number of optical measurements are made to determine overlay accuracy, in order to minimize time delays.
It would therefore be desirable to measure the overlay of respective layers using a technique that does not include the shortcomings and limitations of optical overlay measurement and which accurately and quickly provides overlay measurements of the substrate being processed.